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On the trade-off between power and flexibility of FPGA clock networks
Julien Lamoureux, Steven J. E. Wilton
Article No.: 13
FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by...
This article presents the design of a generic HyperTransport (HT) core. HyperTransport is a packet-based interconnect technology for low-latency, high-bandwidth point-to-point connections. It is specially optimized to achieve a very low latency....
Particle graphics simulations are well suited for modeling complex phenomena such as water, cloth, explosions, fire, smoke, and clouds. They are normally realized in software as part of an interactive graphics application. The computational...
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
David Grant, Guy Lemieux
Article No.: 16
CAD tool designers are always searching for more benchmark circuits to stress their software. In this article we present a heuristic method to generate benchmark circuits specially suited for incremental place-and-route tools. The method removes...
Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures
Pao-Ann Hsiung, Chao-Sheng Lin, Chih-Feng Liao
Article No.: 17
To cope with increasing demands for higher computational power and greater system flexibility, dynamically and partially reconfigurable logic has started to play an important role in embedded systems and systems-on-chip (SoC). However, when using...