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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 1 Issue 4, January 2009

Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
Scott Y. L. Chin, Steven J. E. Wilton
Article No.: 18
DOI: 10.1145/1462586.1462587

This article presents techniques to reduce the static and dynamic memory requirements of routing algorithms that target field-programmable gate arrays. During routing, memory is required to store both architectural data and temporary routing data....

FPGA Acceleration of RankBoost in Web Search Engines
Ning-Yi Xu, Xiong-Fei Cai, Rui Gao, Lei Zhang, Feng-Hsiung Hsu
Article No.: 19
DOI: 10.1145/1462586.1462588

Search relevance is a key measurement for the usefulness of search engines. Shift of search relevance among search engines can easily change a search company's market cap by tens of billions of dollars. With the ever-increasing scale of the Web,...

Searching for Transient Pulses with the ETA Radio Telescope
C. D. Patterson, S. W. Ellingson, B. S. Martin, K. Deshpande, J. H. Simonetti, M. Kavic, S. E. Cutchin
Article No.: 20
DOI: 10.1145/1462586.1462589

Array-based, direct-sampling radio telescopes have computational and communication requirements unsuited to conventional computer and cluster architectures. Synchronization must be strictly maintained across a large number of parallel data...

Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing
Esam El-Araby, Ivan Gonzalez, Tarek El-Ghazawi
Article No.: 21
DOI: 10.1145/1462586.1462590

Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might...

RAT: RC Amenability Test for Rapid Performance Prediction
Brian Holland, Karthik Nagarajan, Alan D. George
Article No.: 22
DOI: 10.1145/1462586.1462591

While the promise of achieving speedup and additional benefits such as high performance per watt with FPGAs continues to expand, chief among the challenges with the emerging paradigm of reconfigurable computing is the complexity in application...

Compute Bound and I/O Bound Cellular Automata Simulations on FPGA Logic
S. Murtaza, A. G. Hoekstra, P. M. A. Sloot
Article No.: 23
DOI: 10.1145/1462586.1462592

FPGA-based computation engines have been used as Cellular Automata accelerators in the scientific community for some time now. With the recent availability of more advanced FPGA logic it becomes necessary to better understand the mapping of...

Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
Christos-S. Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung
Article No.: 24
DOI: 10.1145/1462586.1462593

Many image processing applications require fast convolution of an image with one or more 2D filters. Field-Programmable Gate Arrays (FPGAs) are often used to achieve this goal due to their fine grain parallelism and reconfigurability. However, the...