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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2 Issue 3, September 2009

A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel Emer
Article No.: 16
DOI: 10.1145/1575774.1575775

Computer architects need to run cycle-accurate performance models of processors orders of magnitude faster. We discuss why the speedup on traditional multicores is limited, and why FPGAs represent a good vehicle to achieve a dramatic performance...

FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation
Jason Cong, Yi Zou
Article No.: 17
DOI: 10.1145/1575774.1575776

Lithography simulation, an essential step in design for manufacturability (DFM), is still far from computationally efficient. Most leading companies use large clusters of server computers to achieve acceptable turn-around time. Thus coprocessor...

Packing Techniques for Virtex-5 FPGAs
Taneem Ahmed, Paul D. Kundarewich, Jason H. Anderson
Article No.: 18
DOI: 10.1145/1575774.1575777

Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis, technology mapping and placement. Packing strongly influences circuit speed, density, and power, and in this article, we consider packing in the...

An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
Article No.: 19
DOI: 10.1145/1575774.1575778

To improve FPGA performance for arithmetic circuits that are dominated by multi-input addition operations, an FPGA logic block is proposed that can be configured as a 6:2 or 7:2 compressor. Compressors have been used successfully in...