Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 3 Issue 1, January 2010

A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices
Antonio Roldao, George A. Constantinides
Article No.: 1
DOI: 10.1145/1661438.1661439

Recent developments in the capacity of modern Field Programmable Gate Arrays (FPGAs) have significantly expanded their applications. One such field is the acceleration of scientific computation and one type of calculation that is commonplace in...

Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer with Application
David Dubois, Andrew Dubois, Thomas Boorman, Carolyn Connor, Steve Poole
Article No.: 2
DOI: 10.1145/1661438.1661440

Double precision floating point Sparse Matrix-Vector Multiplication (SMVM) is a critical computational kernel used in iterative solvers for systems of sparse linear equations. The poor data locality exhibited by sparse matrices along with the high...

DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs
Saar Drimer, Tim Güneysu, Christof Paar
Article No.: 3
DOI: 10.1145/1661438.1661441

We present three lookup-table-based AES implementations that efficiently use the BlockRAM and DSP units embedded within Xilinx Virtex-5 FPGAs. An iterative module outputs a 32-bit AES round column every clock cycle, with a throughput of 1.67...

Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
Shannon Koh, Oliver Diessel
Article No.: 4
DOI: 10.1145/1661438.1661442

Partial runtime reconfiguration allows some circuit components to be reconfigured while the remaining circuitry continues to operate. Applications partitioned into modules have the potential to exploit this capability to virtualize hardware by...

Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
John Curreri, Seth Koehler, Alan D. George, Brian Holland, Rafael Garcia
Article No.: 5
DOI: 10.1145/1661438.1661443

High-Level Languages (HLLs) for Field-Programmable Gate Arrays (FPGAs) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling...