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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 3 Issue 3, September 2010

Fast, Efficient Floating-Point Adders and Multipliers for FPGAs
K. Scott Hemmert, Keith D. Underwood
Article No.: 11
DOI: 10.1145/1839480.1839481

Floating-point applications are a growing trend in the FPGA community. As such, it has become critical to create floating-point units optimized for standard FPGA technology. Unfortunately, the FPGA design space is very different from the VLSI...

Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms
Ahmad Sghaier, Shawki Areibi, Robert Dony
Article No.: 12
DOI: 10.1145/1839480.1839482

This work investigates several approaches for implementing the OFDM functions of the fixed-WiMax standard on reconfigurable platforms. In the first phase, a custom RTL approach, using VHDL, is investigated. The approach shows the capability of a...

An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
Article No.: 13
DOI: 10.1145/1839480.1839483

State-of-the-art configurable logic platforms, such as Field-Programmable Gate Arrays (FPGAs), consist of a heterogeneous mixture of different component types. Compared to traditional homogeneous configurable platforms, heterogeneity provides...

Hardware-Accelerated RNA Secondary-Structure Alignment
James Moscola, Ron K. Cytron, Young H. Cho
Article No.: 14
DOI: 10.1145/1839480.1839484

The search for homologous RNA molecules---sequences of RNA that might behave simiarly due to similarity in their physical (secondary) structure---is currently a computationally intensive task. Moreover, RNA sequences are populating genome...

Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs
Yosi Ben-Asher, Danny Meisler, Nadav Rotem
Article No.: 15
DOI: 10.1145/1839480.1839485

In High-Level Synthesis (HLS), extracting parallelism in order to create small and fast circuits is the main advantage of HLS over software execution. Modulo Scheduling (MS) is a technique in which a loop is parallelized by overlapping different...

VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware
Xiaojun Wang, Miriam Leeser
Article No.: 16
DOI: 10.1145/1839480.1839486

Optimal reconfigurable hardware implementations may require the use of arbitrary floating-point formats that do not necessarily conform to IEEE specified sizes. We present a variable precision floating-point library (VFloat) that supports general...

Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis
Madhura Purnaprajna, Mario Porrmann, Ulrich Rueckert, Michael Hussmann, Michael Thies, Uwe Kastens
Article No.: 17
DOI: 10.1145/1839480.1839487

In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates...

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt
Article No.: 18
DOI: 10.1145/1839480.1839488

Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. In an on-demand computing environment, a dynamically invoked application is assigned resources such as data bandwidth, configurable logic. The...