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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4 Issue 1, December 2010

Guest Editorial ARC 2009
Roger Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan
Article No.: 1
DOI: 10.1145/1857927.1857928

An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator
Chalermpol Saiprasert, Christos-S. Bouganis, George A. Constantinides
Article No.: 2
DOI: 10.1145/1857927.1857929

Monte Carlo simulation is one of the most widely used techniques for computationally intensive simulations in mathematical analysis and modeling. A multivariate Gaussian random number generator is one of the main building blocks of such a system....

Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
Article No.: 3
DOI: 10.1145/1857927.1857930

This paper argues the case for the use of analytical models in FPGA architecture exploration. We show that the problem, when simplified, is amenable to formal optimization techniques such as integer linear programming. However, the simplification...

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
K. Kępa, F. Morgan, K. Kościuszkiewicz, L. Braun, M. Hübner, J. Becker
Article No.: 4
DOI: 10.1145/1857927.1857931

The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging...

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core
Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
Article No.: 5
DOI: 10.1145/1857927.1857932

In the present study, we investigate the use of reconfigurable logic devices (RLDs) as intellectual properties (IPs) for system on a chip (SoC). Using RLDs, SoCs can achieve both high performance and high flexibility. However, conventional RLDs...

Optimized System-on-Chip Integration of a Programmable ECC Coprocessor
Xu Guo, Patrick Schaumont
Article No.: 6
DOI: 10.1145/1857927.1857933

Most hardware/software (HW/SW) codesigns of Elliptic Curve Cryptography have focused on the computational aspect of the ECC hardware, and not on the system integration into a System-on-Chip (SoC) architecture. We study the impact of the...

A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
Luca Sterpone
Article No.: 7
DOI: 10.1145/1857927.1857934

Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Simultaneously the computation capabilities required in these fields are constantly...

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications
M. Lanuzza, P. Zicari, F. Frustaci, S. Perri, P. Corsonello
Article No.: 8
DOI: 10.1145/1857927.1857935

This article presents a novel configuration scrubbing core, used for internal detection and correction of radiation-induced configuration single and multiple bit errors, without requiring external scrubbing. The proposed technique combines the...

Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems
Pao-Ann Hsiung, Chun-Hsian Huang, Jih-Sheng Shen, Chen-Chi Chiang
Article No.: 9
DOI: 10.1145/1857927.1857936

With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such...

An Approach for Solving Large SAT Problems on FPGA
Kenji Kanazawa, Tsutomu Maruyama
Article No.: 10
DOI: 10.1145/1857927.1857937

WSAT and its variants are one of the best performing stochastic local search algorithms for the satisfiability (SAT) problem. In this article, we propose an approach for solving large 3-SAT problems on FPGA using a WSAT algorithm. In hardware...

Evaluation of Random Delay Insertion against DPA on FPGAs
Yingxi Lu, Maire O’Neill, John McCanny
Article No.: 11
DOI: 10.1145/1857927.1857938

Side-channel attacks (SCA) threaten electronic cryptographic devices and can be carried out by monitoring the physical characteristics of security circuits. Differential Power Analysis (DPA) is one the most widely studied side-channel attacks....