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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4 Issue 2, May 2011

Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation
Etienne Bergeron, Louis-David Perron, Marc Feeley, Jean Pierre David
Article No.: 12
DOI: 10.1145/1968502.1968503

Just-In-Time (JIT) compilation is frequently used in software engineering to accelerate program execution. Parts of the code are translated to machine code at runtime to speedup their execution by exploiting local and dynamic information of the...

A Novel Multicontext Coarse-Grained Reconfigurable Architecture (CGRA) For Accelerating Column-Oriented Databases
Pranav Vaidya, Jaehwan John Lee
Article No.: 13
DOI: 10.1145/1968502.1968504

The storage model of column-oriented databases is similar in structure to densely packed matrices/vectors found in many high-performance computing applications. Hence, hardware-accelerated vectorized matrix operations using Reconfigurable Logic...

A Scalable and Programmable Modular Traffic Manager Architecture
Shane O’Neill, Roger Francis Woods, Alan James Marshall, Qi Zhang
Article No.: 14
DOI: 10.1145/1968502.1968505

A key issue in the design of next-generation Internet routers and switches will be provision of Traffic Manager (TM) functionality in the datapaths of their high-speed switching fabrics. A new architecture that allows dynamic deployment of...

Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control
Mao Nakajima, Minoru Watanabe
Article No.: 15
DOI: 10.1145/1968502.1968506

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous...

A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning
Tzu-Chiang Tai, Yen-Tai Lai
Article No.: 16
DOI: 10.1145/1968502.1968507

Dynamically reconfigurable FPGAs (DRFPGAs) have high logic utilization because of time-multiplexed interconnects and logic. In this article, we propose a performance-oriented algorithm for the DRFPGA partitioning problem. This algorithm partitions...

Domain-Specific Optimization of Signal Recognition Targeting FPGAs
Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang
Article No.: 17
DOI: 10.1145/1968502.1968508

Domain-specific optimizations on matrix computations exploiting specific arithmetic and matrix representation formats have achieved significant performance/area gains in Field-Programmable Gate Array (FPGA) hardware designs. In this article, we...

The Instruction-Set Extension Problem: A Survey
Carlo Galuzzi, Koen Bertels
Article No.: 18
DOI: 10.1145/1968502.1968509

The extension of a given instruction-set with specialized instructions has become a common technique used to speed up the execution of applications. By identifying computationally intensive portions of an application to be partitioned in segments...

Scientific Application Demands on a Reconfigurable Functional Unit Interface
Kyle Rupnow, Keith D. Underwood, Katherine Compton
Article No.: 19
DOI: 10.1145/1968502.1968510

Modern scientific applications are large, complex, and highly parallel they are commonly executed on supercomputers with tens of thousands of processors. Yet these applications still commonly require weeks or even months to execute. Thus,...

FPGA Acceleration of MultiFactor CDO Pricing
Alexander Kaganov, Asif Lakhany, Paul Chow
Article No.: 20
DOI: 10.1145/1968502.1968511

The last decade has seen a significant growth in the financial industry. The recent widespread use of Internet technology has increased the accessibility of the general population to financial data, thereby increasing the average portfolio size....