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Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
Hanyu Liu, Senthilkumar T. Rajavel, Ali Akoglu
Article No.: 12
In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly...
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies
Gayatri Mehta, Carson Crawford, Xiaozhong Luo, Natalie Parde, Krunalkumar Patel, Brandon Rodgers, Anil Kumar Sistla, Anil Yadav, Marc Reisner
Article No.: 13
The problem of creating efficient mappings of dataflow graphs onto specific architectures (i.e., solving the place and route problem) is incredibly challenging. The difficulty is especially acute in the area of Coarse-Grained Reconfigurable...
Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and...
Analyzing System-Level Information’s Correlation to FPGA Placement
Farnaz Gharibian, Lesley Shannon, Peter Jamieson, Kevin Chung
Article No.: 15
One popular placement algorithms for Field-Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement from a flattened design that no longer contains any high-level information...