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Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs
Franjo Plavec, Zvonko Vranesic, Stephen Brown
Article No.: 16
This article describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook and is based on the existing Brook...
A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator
T. Ananthan, M. V. Vaidyan
Article No.: 17
The self-tuning regulator (STR) is a popular adaptive control algorithm. A high-performance computer is required for its implementation due to the heavy online computational burden. To extend STR for more real-time applications, a parallel...
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
Yoon Kah Leow, Ali Akoglu, Susan Lysecky
Article No.: 18
As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching...
Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies
Yosi Ben-Asher, Ron Meldiner, Nadav Rotem
Article No.: 19
We consider the problem of synthesizing circuits (from C to Verilog) that are optimized to handle unpredictable latencies of memory operations. Unpredictable memory latencies can occur due to the use of on chip caches, DRAM memory modules,...