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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7 Issue 1, February 2014

Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs
George Kornaros, Dionisios Pnevmatikatos
Article No.: 1
DOI: 10.1145/2567658

Advances in silicon process technology have made it possible to include multiple processor cores on a single die. Billion transistor architectures usually in the form of networks-on-chip present a wide range of challenges in design,...

High-Level Abstractions and Modular Debugging for FPGA Design Validation
Yousef Iskander, Cameron Patterson, Stephen Craven
Article No.: 2
DOI: 10.1145/2567662

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide visibility and control of the different stages of a design, many require that the design...

Fast and Accurate Stereo Vision System on FPGA
Minxi Jin, Tsutomu Maruyama
Article No.: 3
DOI: 10.1145/2567659

In this article, we present a fast and high quality stereo matching algorithm on FPGA using cost aggregation (CA) and fast locally consistent (FLC) dense stereo. In many software programs, global matching algorithms are used in order to obtain...

Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda
Article No.: 4
DOI: 10.1145/2567661

The ease-of-use and reconfigurability of FPGAs makes them an attractive platform for accelerating algorithms. However, accelerating becomes a challenging task as the large number of possible design parameters lead to different accelerator...

A Fully Pipelined FPGA Architecture of a Factored Restricted Boltzmann Machine Artificial Neural Network
Lok-Won Kim, Sameh Asaad, Ralph Linsker
Article No.: 5
DOI: 10.1145/2539125

Artificial neural networks (ANNs) are a natural target for hardware acceleration by FPGAs and GPGPUs because commercial-scale applications can require days to weeks to train using CPUs, and the algorithms are highly parallelizable. Previous work...