Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7 Issue 2, June 2014

Section: 1 - Special Section on the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS'12)

Introduction to the TRETS Special Section on the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS'12)
Tobias Becker
Article No.: 11
DOI: 10.1145/2611564

Coordination of Independent Loops in Self-Adaptive Systems
Jacopo Panerati, Martina Maggio, Matteo Carminati, Filippo Sironi, Marco Triverio, Marco D. Santambrogio
Article No.: 12
DOI: 10.1145/2611563

Nowadays, the same piece of code should run on different architectures, providing performance guarantees in a variety of environments and situations. To this end, designers often integrate existing systems with ad-hoc adaptive strategies able to...

Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores
Andreas Agne, Markus Happe, Achim Lösch, Christian Plessl, Marco Platzner
Article No.: 13
DOI: 10.1145/2617596

Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it...

Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs
Christian Beckhoff, Dirk Koch, Jim Torresen
Article No.: 14
DOI: 10.1145/2617597

To fully exploit the capabilities of runtime reconfigurable FPGAs in self-aware systems, design tools are required that exceed the capabilities of present vendor design tools. Such tools must allow the implementation of scalable reconfigurable...

A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems
Xinyu Niu, Qiwei Jin, Wayne Luk, Stephen Weston
Article No.: 15
DOI: 10.1145/2617598

Finite-difference methods are computationally intensive and required by many applications. Parameters of a finite-difference algorithm, such as grid size, can be varied to generate design space which contains algorithm instances with different...

VTR 7.0: Next Generation Architecture and CAD System for FPGAs
Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Anderson, Jonathan Rose, Vaughn Betz
Article No.: 6
DOI: 10.1145/2617593

Exploring architectures for large, modern FPGAs requires sophisticated software that can model and target hypothetical devices. Furthermore, research into new CAD algorithms often requires a complete and open source baseline CAD flow. This article...

Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration
Soumya J., Ashish Sharma, Santanu Chattopadhyay
Article No.: 7
DOI: 10.1145/2556944

This article proposes a reconfigurable Network-on-Chip (NoC) architecture based on mesh topology. It provides a local reconfiguration of cores to connect to any of the neighboring routers, depending upon the currently executing application. The...

FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function
Yuanwu Lei, Lei Guo, Yong Dou, Sheng Ma, Jinbo Xu
Article No.: 8
DOI: 10.1145/2617594

In the current article, the capability and flexibility of field programmable gate-arrays (FPGAs) to implement IEEE-754 double-precision floating-point elementary functions are explored. To perform various elementary functions on the unified...

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms
Juan Antonio Clemente, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto
Article No.: 9
DOI: 10.1145/2611562

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These...

Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA
Anh-Tuan Hoang, Takeshi Fujino
Article No.: 10
DOI: 10.1145/2617595

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs...