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We demonstrate circuits that generate set and integer partitions on a set S of n objects at a rate of one per clock. Partitions are ways to group elements of a set together and have been extensively studied by researchers in...
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
Nuno Paulino, João Canas Ferreira, João M. P. Cardoso
Article No.: 29
This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the...
Associative memories can map sparsely used keys to values with low latency but can incur heavy area overheads. The lack of customized hardware for associative memories in today’s mainstream FPGAs exacerbates the overhead cost of building...
Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing
Daniel Llamocca, Marios Pattichis
Article No.: 31
There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints on energy, performance, and accuracy. The generation of real-time constraints will significantly expand the applicability of...
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction
Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André Dehon
Article No.: 32
Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount...
NCBI BLASTP on High-Performance Reconfigurable Computing Systems
Atabak Mahram, Martin C. Herbordt
Article No.: 33
The BLAST sequence alignment program is a central application in bioinformatics. The de facto standard version, NCBI BLAST, uses complex heuristics that make it challenging to simultaneously achieve both high performance and exact agreement. We...
Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs
Pawel Swierczynski, Amir Moradi, David Oswald, Christof Paar
Article No.: 34
To protect Field-Programmable Gate Array (FPGA) designs against Intellectual Property (IP) theft and related issues such as product cloning, all major FPGA manufacturers offer a mechanism to encrypt the bitstream that is used to configure the...
With the widespread availability of broadband Internet, Field-Programmable Gate Arrays (FPGAs) can get remote updates in the field. This provides hardware and software updates, and enables issue solving and upgrade ability without device...
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems
Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan Maciejowski, Peter Y. K. Cheung, Wayne Luk
Article No.: 36
This article presents an approach for mapping real-time applications based on particle filters (PFs) to heterogeneous reconfigurable systems, which typically consist of multiple FPGAs and CPUs. A method is proposed to adapt the number of particles...
Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation
Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk
Article No.: 37
Physical models utilize mathematical equations to characterize physical systems like airway mechanics, neuron networks, or chemical reactions. Previous work has shown that field programmable gate arrays (FPGAs) execute physical models efficiently....