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ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on the 2014 International Symposium on Applied Reconfigurable Computing, Volume 9 Issue 1, November 2015

Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware
Joonseok Park, Pedro C. Diniz
Article No.: 1
DOI: 10.1145/2751563

There is an increasing concern about transient errors in deep submicron processor architectures. Software-only error detection approaches that exploit program invariants for silent error detection incur large execution overheads and are unreliable...

ARC 2014: A Multidimensional FPGA-Based Parallel DBSCAN Architecture
Neil Scicluna, Christos-Savvas Bouganis
Article No.: 2
DOI: 10.1145/2724722

Clustering large numbers of data points is a very computationally demanding task that often needs to be accelerated in order to be useful in practical applications. This work focuses on the Density-Based Spatial Clustering of Applications with...

Implementing Curve25519 for Side-Channel--Protected Elliptic Curve Cryptography
Pascal Sasdrich, Tim Güneysu
Article No.: 3
DOI: 10.1145/2700834

For security-critical embedded applications Elliptic Curve Cryptography (ECC) has become the predominant cryptographic system for efficient key agreement and digital signatures. However, ECC still involves complex modular arithmetic that is a...

An Enhanced Adaptive Recoding Rotation CORDIC
Jianfeng Zhang, Paul Chow, Hengzhu Liu
Article No.: 4
DOI: 10.1145/2812813

The Conventional Coordinate Rotation Digital Computer (CORDIC) algorithm has been widely used in many applications, particularly in Direct Digital Frequency Synthesizers (DDS) and Fast Fourier Transforms (FFT). However, CORDIC is constrained by...

Section: Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware

Guest Editorial ARC 2014
Diana Goehringer, Marco D. Santambrogio, João M. P. Cardoso, Koen Bertels
Article No.: 5
DOI: 10.1145/2831431

On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip’s Internal Configuration Infrastructure
Karel Heyse, Jente Basteleus, Brahim Al Farisi, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell
Article No.: 6
DOI: 10.1145/2700835

It is common for large hardware designs to have a number of registers or memories whose contents have to be changed very seldom (e.g., only at startup). The conventional way of accessing these memories is through a low-speed memory bus. This bus...

ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation
Rui Policarpo Duarte, Christos-Savvas Bouganis
Article No.: 7
DOI: 10.1145/2818380

Karhunen-Loeve Transformation is a widely used algorithm in signal processing that often implemented with high-throughput requisites. This work presents a novel methodology to optimise KLT designs on FPGAs that outperform typical design...

ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for Image Coding Using a Parallel Index-Aware Tree
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
Article No.: 8
DOI: 10.1145/2766454

The embedded image processing systems like smartphones and digital cameras have tight limits on storage, computation power, network connectivity, and battery usage. These limitations make it important to ensure efficient image coding. In the...