Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on RAW2014, Volume 9 Issue 2, February 2016

CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition
Jianfeng Zhang, Paul Chow, Hengzhu Liu
Article No.: 9
DOI: 10.1145/2827700

Multiple input multiple output (MIMO) with orthogonal frequency division multiplexing (OFDM) systems typically use orthogonal-triangular (QR) decomposition. In this article, we present an enhanced systolic array architecture to realize QR...

Separation Logic for High-Level Synthesis
Felix J. Winterstein, Samuel R. Bayliss, George A. Constantinides
Article No.: 10
DOI: 10.1145/2836169

High-Level Synthesis (HLS) promises a significant shortening of the FPGA design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. However, applications using dynamic, pointer-based data structures...

Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs
Hirak Kashyap, Ricardo Chaves
Article No.: 11
DOI: 10.1145/2816822

The dynamic partial reconfiguration functionality of FPGAs can be attacked, particularly when the FPGA is remotely located or the configuration bitstreams are sent through insecure networks. The existing FPGA technologies provide some built-in...

Coarse-Grained Architecture for Fingerprint Matching
Jinwei Xu, Jingfei Jiang, Yong Dou, Xiaolong Shen, Zhiqiang Liu
Article No.: 12
DOI: 10.1145/2791296

Fingerprint matching is a key procedure in fingerprint identification applications. The minutiae-based fingerprint matching algorithm is one of the most typical algorithms achieving a reasonably correct recognition rate. This study proposes a...

Section: CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition

Guest Editorial RAW 2014
Marco D. Santambrogio, Ramachandran Vaidyanathan
Article No.: 13
DOI: 10.1145/2841314

Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware
Ali Mustafa Zaidi, David Greaves
Article No.: 14
DOI: 10.1145/2807702

Although custom (and reconfigurable) computing can provide orders-of-magnitude improvements in energy efficiency and performance for many numeric, data-parallel applications, performance on nonnumeric, sequential code is often worse than...

RAW 2014: Random Number Generators on FPGAs
Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck
Article No.: 15
DOI: 10.1145/2807699

Random numbers are important ingredients in a number of applications. Especially in a security context, they must be well distributed and unpredictable. We investigate the practical use of random number generators (RNGs) that are built from...

A Reconfigurable Architecture for the Detection of Strongly Connected Components
Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
Article No.: 16
DOI: 10.1145/2807700

The Strongly Connected Components (SCCs) detection algorithm serves as a keystone for many graph analysis applications. The SCC execution time for large-scale graphs, as with many other graph algorithms, is dominated by memory latency. In this...