Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015, Volume 9 Issue 4, September 2016

Section: Regular Papers

A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing
Zain Ul-Abdin, Bertil Svensson
Article No.: 24
DOI: 10.1145/2843946

The future trend in microprocessors for the more advanced embedded systems is focusing on massively parallel reconfigurable architectures, consisting of heterogeneous ensembles of hundreds of processing elements communicating over a reconfigurable...

FPGA-Based Dynamically Reconfigurable SQL Query Processing
Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber
Article No.: 25
DOI: 10.1145/2845087

In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated...

Shared Memory Multicore MicroBlaze System with SMP Linux Support
Eric Matthews, Lesley Shannon, Alexandra Fedorova
Article No.: 26
DOI: 10.1145/2870638

In this work, we present PolyBlaze, a scalable and configurable multicore platform for FPGA-based embedded systems and systems research. PolyBlaze is an extension of the MicroBlaze soft processor, leveraging the configurability of the MicroBlaze...

ODoST: Automatic Hardware Acceleration for Biomedical Model Integration
Ting Yu, Chris Bradley, Oliver Sinnen
Article No.: 27
DOI: 10.1145/2870639

Dynamic biomedical systems are mathematically described by Ordinary Differential Equations (ODEs) and their solution is often one of the most computationally intensive parts in biomedical simulations. With high inherent parallelism, hardware...

Section: Regular Papers

Deming Chen
Article No.: 28
DOI: 10.1145/2955103

Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs
Evan Wegley, Yanhua Yi, Qinhai Zhang
Article No.: 29
DOI: 10.1145/2892640

In addition to optimizing for long-path timing and routability, commercial FPGA routing engines must also optimize for various timing constraints, enabling users to fine tune their designs. These timing constraints involve both long- and...

Impact of Parallelism and Memory Architecture on FPGA Communication Energy
Edin Kadric, David Lakata, André Dehon
Article No.: 30
DOI: 10.1145/2857057

The energy in FPGA computations is dominated by data communication energy, either in the form of memory references or data movement on interconnect. In this article, we explore how to use data placement and parallelism to reduce communication...

Fine-Grained Interconnect Synthesis
Alex Rodionov, David Biancolin, Jonathan Rose
Article No.: 31
DOI: 10.1145/2892641

One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a...