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Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs
André DeHon, Mike Hutton
Article No.: 2
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa
Article No.: 3
A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by intrinsic within-die variation is proposed. The timing variation is reduced by selecting an appropriate configuration for each chip from a...
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs
Satish Sivaswamy, Kia Bazargan
Article No.: 4
With constant scaling of process technologies, chip design is becoming increasingly difficult due to process variations. The FPGA community has only recently started focusing on the effects of variations. In this work we present a statistical...
Advancements in reconfigurable technologies, specifically FPGAs, have yielded faster, more power-efficient reconfigurable devices with enormous capacities. In our work, we provide testament to the impressive capacity of recent FPGAs by hosting a...
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy
Wenyi Feng, Sinan Kaptanoglu
Article No.: 6
In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we...
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
Steven J.E. Wilton, Chun Hok Ho, Bradley Quinton, Philip H.W. Leong, Wayne Luk
Article No.: 7
We present an architecture for a synthesizable datapath-oriented FPGA core that can be used to provide post-fabrication flexibility to an SoC. Our architecture is optimized for bus-based operations and employs a directional routing architecture,...