Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2 Issue 2, June 2009

Hideharu Amano, Tadao Nakamura
Article No.: 7
DOI: 10.1145/1534916.1534917

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA
Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat
Article No.: 8
DOI: 10.1145/1534916.1534918

As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the...

Hardware Decompression Techniques for FPGA-Based Embedded Systems
Dirk Koch, Christian Beckhoff, Jürgen Teich
Article No.: 9
DOI: 10.1145/1534916.1534919

In this work, we present hardware decompression accelerators for widening the bottleneck between slow nonvolatile memories on the one side and high-speed FPGA configuration interfaces and fast softcore CPUs on the other side. We discuss different...

Self-Measurement of Combinatorial Circuit Delays in FPGAs
Justin S. J. Wong, Pete Sedcole, Peter Y. K. Cheung
Article No.: 10
DOI: 10.1145/1534916.1534920

This article proposes a Built-In Self-Test (BIST) method to accurately measure the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of...

Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits
G. Seetharaman, B. Venkataramani
Article No.: 11
DOI: 10.1145/1534916.1534921

Operating frequencies of combinational logic circuits can be increased using Wave-Pipelining (WP), by adjusting the clock periods and clock skews. In this article, Built-In Self-Test (BIST) and System-on-Chip (SOC) approaches are proposed for...

Vector Processing as a Soft Processor Accelerator
Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy Lemieux
Article No.: 12
DOI: 10.1145/1534916.1534922

Current FPGA soft processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft vector processor as a general-purpose accelerator. The approach...

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Hosein Seyed Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gurkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
Article No.: 13
DOI: 10.1145/1534916.1534923

Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In...

WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging
Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko
Article No.: 14
DOI: 10.1145/1534916.1534924

This article presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of...

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs
Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi
Article No.: 15
DOI: 10.1145/1534916.1534925

Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is limited throughput when simulating large multiprocessor systems...