Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 3 Issue 4, November 2010

Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration
Jason Williams, Chris Massie, Alan D. George, Justin Richardson, Kunal Gosrani, Herman Lam
Article No.: 19
DOI: 10.1145/1862648.1862649

As on-chip transistor counts increase, the computing landscape has shifted to multi- and many-core devices. Computational accelerators have adopted this trend by incorporating both fixed and reconfigurable many-core and multi-core devices. As...

Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing
Miaoqing Huang, Vikram K. Narayana, Harald Simmler, Olivier Serres, Tarek El-Ghazawi
Article No.: 20
DOI: 10.1145/1862648.1862650

High-performance reconfigurable computing involves acceleration of significant portions of an application using reconfigurable hardware. When the hardware tasks of an application cannot simultaneously fit in an FPGA, the task graph needs to be...

FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods
Kentaro Sano, Wang Luzhou, Yoshiaki Hatsuda, Takanori Iizuka, Satoru Yamamoto
Article No.: 21
DOI: 10.1145/1862648.1862651

For scientific numerical simulation that requires a relatively high ratio of data access to computation, the scalability of memory bandwidth is the key to performance improvement, and therefore custom-computing machines (CCMs) are one of the...

MPI as a Programming Model for High-Performance Reconfigurable Computers
Manuel Saldaña, Arun Patel, Christopher Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam
Article No.: 22
DOI: 10.1145/1862648.1862652

High-Performance Reconfigurable Computers (HPRCs) consist of one or more standard microprocessors tightly-coupled with one or more reconfigurable FPGAs. HPRCs have been shown to provide good speedups and good cost/performance ratios, but not...

Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems
Matt Chiu, Martin C. Herbordt
Article No.: 23
DOI: 10.1145/1862648.1862653

The acceleration of molecular dynamics (MD) simulations using high-performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore and GPUs, there is now a question whether MD on HPRC can be...

Placement and Floorplanning in Dynamically Reconfigurable FPGAs
Alessio Montone, Marco D. Santambrogio, Donatella Sciuto, Seda Ogrenci Memik
Article No.: 24
DOI: 10.1145/1862648.1862654

The aim of this article is to describe a complete partitioning and floorplanning algorithm tailored for reconfigurable architectures deployable on FPGAs and considering communication infrastructure feasibility. This article proposes a novel...

A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems
Casey Reardon, Eric Grobelny, Alan D. George, Gongyu Wang
Article No.: 25
DOI: 10.1145/1862648.1862655

Reconfigurable computing (RC) is rapidly emerging as a promising technology for the future of high-performance and embedded computing, enabling systems with the computational density and power of custom-logic hardware and the versatility of...

High-Performance Quasi-Monte Carlo Financial Simulation: FPGA vs. GPP vs. GPU
Xiang Tian, Khaled Benkrid
Article No.: 26
DOI: 10.1145/1862648.1862656

Quasi-Monte Carlo simulation is a special Monte Carlo simulation method that uses quasi-random or low-discrepancy numbers as random sample sets. In many applications, this method has proved advantageous compared to the traditional Monte Carlo...