Reconfigurable Technology and Systems (TRETS)


Search Issue
enter search term and/or author name


ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4 Issue 4, December 2011

Introduction to special section FPGA 2009
Peter Y.K. Cheung
Article No.: 31
DOI: 10.1145/2068716.2068717

VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Kenneth Kent, Jonathan Rose
Article No.: 32
DOI: 10.1145/2068716.2068718

The VPR toolset has been widely used in FPGA architecture and CAD research, but has not evolved over the past decade. This article describes and illustrates the use of a new version of the toolset that includes four new features: first, it...

Choose-your-own-adventure routing: Lightweight load-time defect avoidance
Raphael Rubin, André Dehon
Article No.: 33
DOI: 10.1145/2068716.2068719

Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation,...

Scalable don't-care-based logic optimization and resynthesis
Alan Mishchenko, Robert Brayton, Jie-Hong R. Jiang, Stephen Jang
Article No.: 34
DOI: 10.1145/2068716.2068720

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization...

FPGA technology mapping with encoded libraries and staged priority cuts
Andrew Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox
Article No.: 35
DOI: 10.1145/2068716.2068721

Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. This article considers enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of...

Performance of partial reconfiguration in FPGA systems: A survey and a cost model
Kyprianos Papadimitriou, Apostolos Dollas, Scott Hauck
Article No.: 36
DOI: 10.1145/2068716.2068722

Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors...

Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA
Xiaoheng Chen, Venkatesh Akella
Article No.: 37
DOI: 10.1145/2068716.2068723

We explore the use of Data-Level Parallelism (DLP) as a way of improving the energy efficiency and power consumption involved in running applications on an FPGA. We show that static power consumption is a significant fraction of the overall power...

Net-length-based routability-driven power-aware clustering
Lakshmi Easwaran, Ali Akoglu
Article No.: 38
DOI: 10.1145/2068716.2068724

The state-of-the-art power-aware clustering tool, P-T-VPack, achieves energy reduction by localizing nets with high switching activity at the expense of channel width and area. In this study, we employ predicted individual postplacement net length...

Compressor tree synthesis on commercial high-performance FPGAs
Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne
Article No.: 39
DOI: 10.1145/2068716.2068725

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR...

Test compression for dynamically reconfigurable processors
Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Masato Motomura, Koichiro Furuta
Article No.: 40
DOI: 10.1145/2068716.2068726

We present the world's first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7...