Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 5 Issue 3, October 2012

Introduction to the Special Issue on ReCoSoC 2011
Michael Hübner
Article No.: 11
DOI: 10.1145/2362374.2362375

Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance
John Shield, Jean-Philippe Diguet, Guy Gogniat
Article No.: 12
DOI: 10.1145/2362374.2362376

Asymmetric coherency is a new optimization method for coherency policies to support nonuniform workloads in multicore processors. Asymmetric coherency assists in load balancing a workload and this is applicable to SoC multicores where the...

Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers
Benjamin Thielmann, Jens Huthmann, Andreas Koch
Article No.: 13
DOI: 10.1145/2362374.2362377

Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a...

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications
Laurent Gantel, Amel Khiar, Benoit Miramond, Mohamed El Amine Benkhelifa, Lounis Kessal, Fabrice Lemonnier, Jimmy Le Rhun
Article No.: 14
DOI: 10.1145/2362374.2362378

Recent FPGAs allow the design of efficient and complex Heterogeneous Systems-on-Chip (HSoC). Namely, these systems are composed of several processors, hardware accelerators as well as communication media between all these components....

A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks
Angelo Kuti Lusala, Jean-Didier Legat
Article No.: 15
DOI: 10.1145/2362374.2362379

This article proposes a circuit-switched router that combines Spatial Division Multiplexing (SDM) and Time Division Multiplexing (TDM) in order to increase path diversity in the router while sharing channels among multiple connections. In this...

Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities
Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Robert Fouquet
Article No.: 16
DOI: 10.1145/2362374.2362380

In data security systems, general purpose processors (GPPs) are often extended by a cryptographic accelerator. The article presents three ways of extending GPPs for symmetric key cryptography applications. Proposed extensions guarantee secure key...

Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization
Luciano Ost, Sameer Varyani, Leandro Soares Indrusiak, Marcelo Mandelli, Gabriel Marchesan Almeida, Eduardo Wachter, Fernando Moraes, Gilles Sassatelli
Article No.: 17
DOI: 10.1145/2362374.2362381

This article explores the use of virtualization to enable mechanisms like task migration and dynamic mapping in heterogeneous MPSoCs, thereby targeting the design of systems capable of adapt their behavior to time-changing workloads. Because tasks...

Remote FPGA Lab for Enhancing Learning of Digital Systems
Fearghal Morgan, Seamus Cawley, David Newell
Article No.: 18
DOI: 10.1145/2362374.2362382

Learning in digital systems can be enhanced through applying a learn-by-doing approach on practical hardware systems and by using Web-based technology to visualize and animate hardware behavior. The authors have reported the Web-based Remote FPGA...