Reconfigurable Technology and Systems (TRETS)


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ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Issue on 11th International Conference on Field-Programmable Technology (FPT'12) and Special Issue on the 7th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC'12), Volume 7 Issue 3, August 2014

Composing Multi-Ported Memories on FPGAs
Charles Eric Laforest, Zimo Li, Tristan O'rourke, Ming G. Liu, J. Gregory Steffan
Article No.: 16
DOI: 10.1145/2629629

Multi-ported memories are challenging to implement on FPGAs since the block RAMs included in the fabric typically have only two ports. Hence we must construct memories requiring more than two ports, either out of logic elements or by combining...

Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications
Yuanxi Peng, Manuel Saldaña, Christopher A. Madill, Xiaofeng Zou, Paul Chow
Article No.: 17
DOI: 10.1145/2629470

MPI has been used as a parallel programming model for supercomputers and clusters and recently in MultiProcessor Systems-on-Chip (MPSoC). One component of MPI is collective communication and its performance is key for certain parallel applications...

Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12)
Jason Anderson, Kiyoung Choi
Article No.: 18
DOI: 10.1145/2655712

The iDEA DSP Block-Based Soft Processor for FPGAs
Hui Yan Cheah, Fredrik Brosser, Suhaib A. Fahmy, Douglas L. Maskell
Article No.: 19
DOI: 10.1145/2629443

DSP blocks in modern FPGAs can be used for a wide range of arithmetic functions, offering increased performance while saving logic resources for other uses. They have evolved to better support a plethora of signal processing tasks, meaning that in...

Networks-on-Chip for FPGAs: Hard, Soft or Mixed?
Mohamed S. Abdelfattah, Vaughn Betz
Article No.: 20
DOI: 10.1145/2629442

As FPGA capacity increases, a growing challenge is connecting ever-more components with the current low-level FPGA interconnect while keeping designers productive and on-chip communication efficient. We propose augmenting FPGAs with...

Graph Minor Approach for Application Mapping on CGRAs
Liang Chen, Tulika Mitra
Article No.: 21
DOI: 10.1145/2655242

Coarse-Grained Reconfigurable Arrays (CGRAs) exhibit high performance, improved flexibility, low cost, and power efficiency for various application domains. Compute-intensive loop kernels, which are perfect candidates to be executed on CGRAs, are...

ULP-SRP: Ultra Low-Power Samsung Reconfigurable Processor for Biomedical Applications
Changmoo Kim, Mookyoung Chung, Yeongon Cho, Mario Konijnenburg, Soojung Ryu, Jeongwook Kim
Article No.: 22
DOI: 10.1145/2629610

The latest biomedical applications require low energy consumption, high performance, and wide energy-performance scalability to adapt to various working environments. In this study, we present ULP-SRP, an energy-efficient reconfigurable processor...

Introduction to the Special Issue on the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'12)
Nikolaos Voros, Guy Gogniat
Article No.: 23
DOI: 10.1145/2655710

RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs
Christian Brugger, Dominic Hillenbrand, Matthias Balzer
Article No.: 24
DOI: 10.1145/2655238

For high-performance embedded hard-real-time systems, ASICs and FPGAs hold advantages over general-purpose processors and graphics accelerators (GPUs). However, developing signal processing architectures from scratch requires significant...

Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems
Fábio Itturiet, Gabriel Nazar, Ronaldo Ferreira, Álvaro Moreira, Luigi Carro
Article No.: 25
DOI: 10.1145/2556943

This article introduces the resilient adaptive algebraic architecture that aims at adapting parallelism exploitation of a matrix multiplication algorithm in a time-deterministic fashion to reduce power consumption while meeting real-time deadlines...

Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration
Siew-Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
Article No.: 26
DOI: 10.1145/2655240

Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the performance benefits of reconfigurable processors that support...

Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling
Sébastien Guillet, Florent de Lamotte, Nicolas le Griguer, Éric Rutten, Guy Gogniat, Jean-Philippe Diguet
Article No.: 27
DOI: 10.1145/2629628

This article presents the first framework to design and synthesize a formal controller managing dynamic reconfiguration, using a model-driven engineering methodology based on an extension of UML/MARTE. The implementation technique highlights the...