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The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Brown, Jason Anderson
Article No.: 14
We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated field-programmable gate array (FPGA) hardware. Using an HLS tool implemented within the state-of-the-art LLVM compiler, we study the effect of...
A design approach is proposed to automatically identify and exploit runtime reconfiguration opportunities with optimised resource utilisation by eliminating idle functions. We introduce Reconfiguration Data Flow Graph, a hierarchical graph...
Exploiting FPGA Block Memories for Protected Cryptographic Implementations
Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He
Article No.: 16
Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs...
CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design
Juan Fernando Eusse, Christopher Williams, Rainer Leupers
Article No.: 17
Application-Specific Instruction Set Processors (ASIPs) provide the adequate performance/efficiency tradeoff for their particular application domain. Nevertheless, their design methodologies have stagnated during the past decade and are still...
Execution Trace--Driven Energy-Reliability Optimization for Multimedia MPSoCs
Anup Das, Amit Kumar Singh, Akash Kumar
Article No.: 18
Multiprocessor systems-on-chip (MPSoCs) are becoming a popular design choice in current and future technology nodes to accommodate the heterogeneous computing demand of a multitude of applications enabled on these platform. Streaming multimedia...
With an increasing number of processing elements (PEs) integrated on a single chip, fault-tolerant techniques are critical to ensure the reliability of such complex systems. In current reconfigurable architectures, redundant PEs are utilized for...
Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware
Roland Dobai, Lukas Sekanina
Article No.: 20
Field-programmable gate arrays (FPGAs) can be considered to be the most popular and successful platform for evolvable hardware. They allow one to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware...